Members of the Computer Engineering Group
| Name | Phone | Room | |
| Professors | |||
| Prof. Dr. Marco Platzner | platzner[at]upb.de | +49 (0) 5251 / 60 5250 | O3.207 |
| Jun.-Prof. Dr. Christian Plessl (PC2) | christian.plessl@uni-paderborn.de | +49 (0) 5251 / 60 5399 | O3.110 |
| Administration | |||
| Paraskewi Antoniou | antoniou[at]mail.uni-paderborn.de | +49 (0) 5251 / 60 5394 | O3.107 |
| Technical Service | |||
| Alfred Maier | amaier[at]upb.de | +49 (0) 5251 / 60 1744 | O3.134 |
| Research Associates | |||
| Dipl.-Inf. Andreas Agne | agne[at]upb.de | +49 (0) 5251 / 60 4348 | O3.125 |
| Jahanzeb Anwer, MSc. (IGS) | jahanzeb.anwer[at]upb.de | +49 (0) 5251 / 60 4342 | O 3.128 |
| Tobias Beisel, MSc. (PC2) | tbeisel[at]upb.de | +49 (0) 5251 / 60 4344 | O3.116 |
| Dipl.-Inf. Alexander Boschmann | alexander.boschmann[at]upb.de | +49 (0) 5251 / 60 5397 | O3.131 |
| Dipl.-Inf. Stephanie Drzevitzky (IGS) | stephanie.drzevitzky[at]upb.de | +49 (0) 5251 / 60 5396 | O3.122 |
| Dipl.-Inf. Heiner Giefers | hgiefers[at]upb.de | +49 (0) 5251 / 60 5395 | O3.122 |
| Markus Happe, MSc. (IGS) | markus.happe[at]upb.de | +49 (0) 5251 / 60 4346 | O3.125 |
| Dipl.-Inf. Dipl.-Math. Paul Kaufmann | paul.kaufmann[at]upb.de | +49 (0) 5251 / 60 5398 | O3.131 |
| Sebastian Meisner | sebastian.meisner[at]upb.de | +49 (0) 5251 / 60 4347 | O3.128 |
| Dipl.-Inf. Lars Schäfers (PC2) | slars[at]upb.de | +49 (0) 5251 / 60 4341 | O3.119 |
| Dipl.-Inf. Tobias Kenter (PC2) | kenter[at]upb.de | +49 (0) 5251 / 60 4340 | O3.119 |
| tobias.wiersema[at]upb.de | +49 (0) 5251 / 60 4343 | O3.116 | |
| Student Assistants | |||
| Denis Dridger | +49 (0) 5251 / 60 2984 | O3.255 | |
| Viktor Gottfried, BSc. | +49 (0) 5251 / 60 2984 | O3.255 | |
| Christoph Rüthing | +49 (0) 5251 / 60 2984 | O3.255 | |
| Krishna Sudhakar, B.E. | +49 (0) 5251 / 60 2984 | O3.255 | |
| Hendrik Kassner | +49 (0) 5251 / 60 2984 | O3.255 | |
| Former PhDs | Thesis | Present Position |
| Rolf Enzler | Architectural trade-offs in dynamically reconfigurable processors | Systems Engineer, Phonak, Switzerland |
| Herbert Walder | Operating system design for partiallly reconfigurable logic devices | Head of Basic Infrastructure, Swisscom, Switzerland |
| Christian Plessl | Hardware virtualization on a coarse-grained reconfigurable processor | Research Associate, Paderborn Center for Parallel Computing, Germany |
| Klaus Danne | Real-time multitasking in embedded systems based on reconfigurable hardware | Component Design Engineer, Intel Microprocessor Technology Lab, Germany |
| Enno Lübbers | Multithreaded programming and execution models for Reconfigurable Hardware | Research Scientist, Intel Labs Europe, Germany |
| Tobias Schumacher | Performance Modeling and Analysis in High-Performance Reconfigurable Computing | Compiler Engineer, Maxeler Technologies, United Kingdom |
| Mariusz Grad | Just-in-Time Processor Customization - on the Feasibility and Limitations of FPGA-based Dynamically Reconfigurable Instruction Set Architectures | FPGA Developer, Fiberblaze A/S, Denmark |
| Other Former Group Members | ||
| Jason Agron, MSc. | ||
| Prof. Dr. David Andrews | ||
| Daniel Breitlauch | ||
| Raymund Hake | ||
| Tobias Knieper | ||
| Alexander Kujat | ||
| Sven Kurras | ||
| Tanja Langen | ||
| Dipl.-Inf. Jens Lischka | ||
| Dipl.-Inf. Robert Meiche | ||
| Dipl.-Ing. Björn Meyer | ||
| Elmar Weber | ||